/*
 * Copyright (C) 2017 Spreadtrum Communications Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2017-12-27 15:24:15
 *
 */


#ifndef ANLG_PHY_G4_H
#define ANLG_PHY_G4_H

#define CTL_BASE_ANLG_PHY_G4 0x40359000


#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_CTRL0                 ( CTL_BASE_ANLG_PHY_G4 + 0x0000 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_CTRL1                 ( CTL_BASE_ANLG_PHY_G4 + 0x0004 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_CTRL2                 ( CTL_BASE_ANLG_PHY_G4 + 0x0008 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_CTRL3                 ( CTL_BASE_ANLG_PHY_G4 + 0x000C )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_CTRL4                 ( CTL_BASE_ANLG_PHY_G4 + 0x0010 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_CTRL0                 ( CTL_BASE_ANLG_PHY_G4 + 0x0018 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_CTRL1                 ( CTL_BASE_ANLG_PHY_G4 + 0x001C )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_CTRL2                 ( CTL_BASE_ANLG_PHY_G4 + 0x0020 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_CTRL3                 ( CTL_BASE_ANLG_PHY_G4 + 0x0024 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_CTRL4                 ( CTL_BASE_ANLG_PHY_G4 + 0x0028 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_CTRL0                 ( CTL_BASE_ANLG_PHY_G4 + 0x0030 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_CTRL1                 ( CTL_BASE_ANLG_PHY_G4 + 0x0034 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_CTRL2                 ( CTL_BASE_ANLG_PHY_G4 + 0x0038 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_CTRL3                 ( CTL_BASE_ANLG_PHY_G4 + 0x003C )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_CTRL4                 ( CTL_BASE_ANLG_PHY_G4 + 0x0040 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL_TEST_CTRL              ( CTL_BASE_ANLG_PHY_G4 + 0x0048 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM1_CTRL_0                 ( CTL_BASE_ANLG_PHY_G4 + 0x004C )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM1_CTRL_1                 ( CTL_BASE_ANLG_PHY_G4 + 0x0050 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_ANA_MPLL_DUMY               ( CTL_BASE_ANLG_PHY_G4 + 0x0054 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_REG_SEL_CFG_0               ( CTL_BASE_ANLG_PHY_G4 + 0x0058 )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXCLKLANE          ( CTL_BASE_ANLG_PHY_G4 + 0x005C )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATA_0           ( CTL_BASE_ANLG_PHY_G4 + 0x0060 )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATA_1           ( CTL_BASE_ANLG_PHY_G4 + 0x0064 )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATA_2           ( CTL_BASE_ANLG_PHY_G4 + 0x0068 )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATA_3           ( CTL_BASE_ANLG_PHY_G4 + 0x006C )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATAESC          ( CTL_BASE_ANLG_PHY_G4 + 0x0070 )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_STATE_RX           ( CTL_BASE_ANLG_PHY_G4 + 0x0074 )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_ERR                ( CTL_BASE_ANLG_PHY_G4 + 0x0078 )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_CTRL               ( CTL_BASE_ANLG_PHY_G4 + 0x007C )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_RSVD               ( CTL_BASE_ANLG_PHY_G4 + 0x0080 )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_TEST               ( CTL_BASE_ANLG_PHY_G4 + 0x0084 )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_DATALANE_CTRL      ( CTL_BASE_ANLG_PHY_G4 + 0x0088 )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_DUMY_CTRL             ( CTL_BASE_ANLG_PHY_G4 + 0x008C )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_REG_SEL_CFG_0             ( CTL_BASE_ANLG_PHY_G4 + 0x0090 )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_REG_SEL_CFG_1             ( CTL_BASE_ANLG_PHY_G4 + 0x0094 )
#define REG_ANLG_PHY_G4_ANALOG_USB20_USB20_TEST_PIN                     ( CTL_BASE_ANLG_PHY_G4 + 0x0098 )
#define REG_ANLG_PHY_G4_ANALOG_USB20_USB20_UTMI_CTL1                    ( CTL_BASE_ANLG_PHY_G4 + 0x009C )
#define REG_ANLG_PHY_G4_ANALOG_USB20_USB20_BATTER_PLL                   ( CTL_BASE_ANLG_PHY_G4 + 0x00A0 )
#define REG_ANLG_PHY_G4_ANALOG_USB20_USB20_UTMI_CTL2                    ( CTL_BASE_ANLG_PHY_G4 + 0x00A4 )
#define REG_ANLG_PHY_G4_ANALOG_USB20_USB20_TRIMMING                     ( CTL_BASE_ANLG_PHY_G4 + 0x00A8 )
#define REG_ANLG_PHY_G4_ANALOG_USB20_USB20_PHY_BIST_TEST                ( CTL_BASE_ANLG_PHY_G4 + 0x00AC )
#define REG_ANLG_PHY_G4_ANALOG_USB20_REG_SEL_CFG_0                      ( CTL_BASE_ANLG_PHY_G4 + 0x00B0 )
#define REG_ANLG_PHY_G4_ANALOG_RCO100M_RTC100M_CTRL                     ( CTL_BASE_ANLG_PHY_G4 + 0x00B4 )
#define REG_ANLG_PHY_G4_ANALOG_RCO100M_REG_SEL_CFG_0                    ( CTL_BASE_ANLG_PHY_G4 + 0x00B8 )
#define REG_ANLG_PHY_G4_ANALOG_USB20_IDDG                               ( CTL_BASE_ANLG_PHY_G4 + 0x00BC )
#define REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_ISO_SW_EN          ( CTL_BASE_ANLG_PHY_G4 + 0x00C0 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_0                ( CTL_BASE_ANLG_PHY_G4 + 0x00C4 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_1                ( CTL_BASE_ANLG_PHY_G4 + 0x00C8 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_2                ( CTL_BASE_ANLG_PHY_G4 + 0x00CC )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_3                ( CTL_BASE_ANLG_PHY_G4 + 0x00D0 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_4                ( CTL_BASE_ANLG_PHY_G4 + 0x00D4 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_5                ( CTL_BASE_ANLG_PHY_G4 + 0x00D8 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_0                ( CTL_BASE_ANLG_PHY_G4 + 0x00DC )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_1                ( CTL_BASE_ANLG_PHY_G4 + 0x00E0 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_2                ( CTL_BASE_ANLG_PHY_G4 + 0x00E4 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_3                ( CTL_BASE_ANLG_PHY_G4 + 0x00E8 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_4                ( CTL_BASE_ANLG_PHY_G4 + 0x00EC )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_5                ( CTL_BASE_ANLG_PHY_G4 + 0x00F0 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_DVFS_0                ( CTL_BASE_ANLG_PHY_G4 + 0x00F4 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_DVFS_1                ( CTL_BASE_ANLG_PHY_G4 + 0x00F8 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_DVFS_2                ( CTL_BASE_ANLG_PHY_G4 + 0x00FC )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_DVFS_3                ( CTL_BASE_ANLG_PHY_G4 + 0x0100 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_DVFS_4                ( CTL_BASE_ANLG_PHY_G4 + 0x0104 )
#define REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_DVFS_5                ( CTL_BASE_ANLG_PHY_G4 + 0x0108 )

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_CTRL0 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_MACRO_TYPE(x)              (((x) & 0xFF) << 24)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_REG_VERSION(x)             (((x) & 0xF) << 20)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_N(x)                       (((x) & 0x7FF) << 8)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_IBIAS(x)                   (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_LPF(x)                     (((x) & 0x7) << 3)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_SDM_EN                     BIT(2)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_MOD_EN                     BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_DIV_S                      BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_CTRL1 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_NINT(x)                    (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_KINT(x)                    (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_CTRL2 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_LOCK_DONE                  BIT(31)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_RST                        BIT(25)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_PD                         BIT(24)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV                    BIT(16)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_CLKOUTDIV_EN               BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_CLKOUT_EN                  BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_CTRL3 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_RESERVED(x)                (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_CCS_CTRL(x)                (((x) & 0xFF))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_CTRL4 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_BIST_CTRL(x)               (((x) & 0xFF) << 17)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_BIST_EN                    BIT(16)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_BIST_CNT(x)                (((x) & 0xFFFF))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_CTRL0 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_MACRO_TYPE(x)              (((x) & 0xFF) << 24)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_REG_VERSION(x)             (((x) & 0xF) << 20)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_N(x)                       (((x) & 0x7FF) << 8)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_IBIAS(x)                   (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_LPF(x)                     (((x) & 0x7) << 3)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_SDM_EN                     BIT(2)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_MOD_EN                     BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_DIV_S                      BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_CTRL1 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_NINT(x)                    (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_KINT(x)                    (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_CTRL2 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_LOCK_DONE                  BIT(31)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_RST                        BIT(25)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_PD                         BIT(24)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV                    BIT(16)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_CLKOUTDIV_EN               BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_CLKOUT_EN                  BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_CTRL3 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_RESERVED(x)                (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_CCS_CTRL(x)                (((x) & 0xFF))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_CTRL4 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_BIST_CTRL(x)               (((x) & 0xFF) << 17)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_BIST_EN                    BIT(16)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_BIST_CNT(x)                (((x) & 0xFFFF))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_CTRL0 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_MACRO_TYPE(x)              (((x) & 0xFF) << 24)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_REG_VERSION(x)             (((x) & 0xF) << 20)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_N(x)                       (((x) & 0x7FF) << 8)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_IBIAS(x)                   (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_LPF(x)                     (((x) & 0x7) << 3)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_SDM_EN                     BIT(2)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_MOD_EN                     BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_DIV_S                      BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_CTRL1 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_NINT(x)                    (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_KINT(x)                    (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_CTRL2 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_LOCK_DONE                  BIT(31)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_RST                        BIT(25)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_PD                         BIT(24)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_POSTDIV                    BIT(16)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_CLKOUTDIV_EN               BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_CLKOUT_EN                  BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_CTRL3 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_RESERVED(x)                (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_CCS_CTRL(x)                (((x) & 0xFF))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_CTRL4 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_BIST_CTRL(x)               (((x) & 0xFF) << 17)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_BIST_EN                    BIT(16)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_BIST_CNT(x)                (((x) & 0xFFFF))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL_TEST_CTRL */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_TEST_SEL(x)                      (((x) & 0x3) << 13)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_TEST_CLK_EN                      BIT(12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_TEST_THM_SEL                     BIT(11)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_ANALOG_PLL_RESERVED(x)           (((x) & 0x7FF))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM1_CTRL_0 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM_BJT_SEL                      BIT(15)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM_RSTN                         BIT(14)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM_RUN                          BIT(13)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM_PD                           BIT(12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM_DATA(x)                      (((x) & 0xFF) << 4)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM_VALID                        BIT(3)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM_BG_RBIAS_MODE                BIT(2)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM_TEST_SEL(x)                  (((x) & 0x3))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM1_CTRL_1 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM_BP_MODE                      BIT(24)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM_BP_DATA(x)                   (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_THM_RESERVED(x)                  (((x) & 0xFFFF))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_ANA_MPLL_DUMY */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_ANALOG_MPLL_DUMY_IN(x)           (((x) & 0xFFFF) << 16)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_ANALOG_MPLL_DUMY_OUT(x)          (((x) & 0xFFFF))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL0_PD                 BIT(15)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL0_RST                BIT(14)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL0_CLKOUTDIV_EN       BIT(13)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL0_CLKOUT_EN          BIT(12)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL1_PD                 BIT(11)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL1_RST                BIT(10)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL1_CLKOUTDIV_EN       BIT(9)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL1_CLKOUT_EN          BIT(8)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL2_PD                 BIT(7)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL2_RST                BIT(6)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL2_CLKOUTDIV_EN       BIT(5)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL2_CLKOUT_EN          BIT(4)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_THM_BJT_SEL              BIT(3)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_THM_RSTN                 BIT(2)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_THM_RUN                  BIT(1)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MPLL_THM_TOP_THM_PD                   BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXCLKLANE */

#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTHSCLK             BIT(4)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSCLK                  BIT(3)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXITCLK              BIT(2)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_STOPSTATECLK               BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ULPSACTIVENOTCLK           BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATA_0 */

#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_0          BIT(10)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_0             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXLPDTESC_0                BIT(8)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_0                BIT(7)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_0               BIT(6)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXTRIGGERESC_0(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXVALIDESC_0               BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXREADYESC_0               BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATA_1 */

#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_1          BIT(10)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_1             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXLPDTESC_1                BIT(8)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_1                BIT(7)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_1               BIT(6)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXTRIGGERESC_1(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXVALIDESC_1               BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXREADYESC_1               BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATA_2 */

#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_2          BIT(10)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_2             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXLPDTESC_2                BIT(8)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_2                BIT(7)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_2               BIT(6)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXTRIGGERESC_2(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXVALIDESC_2               BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXREADYESC_2               BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATA_3 */

#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_3          BIT(10)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_3             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXLPDTESC_3                BIT(8)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_3                BIT(7)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_3               BIT(6)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXTRIGGERESC_3(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXVALIDESC_3               BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXREADYESC_3               BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATAESC */

#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXDATAESC_0(x)             (((x) & 0xFF) << 24)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXDATAESC_1(x)             (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXDATAESC_2(x)             (((x) & 0xFF) << 8)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TXDATAESC_3(x)             (((x) & 0xFF))

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_STATE_RX */

#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXCLKESC_0                 BIT(27)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXLPDTESC_0                BIT(26)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXTRIGGERESC_0(x)          (((x) & 0xF) << 22)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXVALIDESC_0               BIT(21)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXCLKESC_1                 BIT(20)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXLPDTESC_1                BIT(19)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXTRIGGERESC_1(x)          (((x) & 0xF) << 15)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXVALIDESC_1               BIT(14)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXCLKESC_2                 BIT(13)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXLPDTESC_2                BIT(12)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXTRIGGERESC_2(x)          (((x) & 0xF) << 8)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXVALIDESC_2               BIT(7)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXCLKESC_3                 BIT(6)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXLPDTESC_3                BIT(5)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXTRIGGERESC_3(x)          (((x) & 0xF) << 1)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RXVALIDESC_3               BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_ERR */

#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRESC_0                   BIT(19)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRSYNCESC_0               BIT(18)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTROL_0               BIT(17)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP0_0         BIT(16)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP1_0         BIT(15)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRESC_1                   BIT(14)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRSYNCESC_1               BIT(13)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTROL_1               BIT(12)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP0_1         BIT(11)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP1_1         BIT(10)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRESC_2                   BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRSYNCESC_2               BIT(8)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTROL_2               BIT(7)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP0_2         BIT(6)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP1_2         BIT(5)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRESC_3                   BIT(4)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRSYNCESC_3               BIT(3)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTROL_3               BIT(2)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP0_3         BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP1_3         BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_CTRL */

#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_PS_PD_S                    BIT(21)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_PS_PD_L                    BIT(20)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_SHUTDOWNZ                  BIT(19)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RSTZ                       BIT(18)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_0                   BIT(17)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_1                   BIT(16)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_2                   BIT(15)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_3                   BIT(14)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ENABLECLK                  BIT(13)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_FORCEPLL                   BIT(12)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_PLLLOCK                    BIT(11)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_BISTON                     BIT(10)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_BISTDONE                   BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_IF_SEL                     BIT(8)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TRIMBG(x)                  (((x) & 0xF) << 4)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TX_RCTL(x)                 (((x) & 0xF))

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_RSVD */

#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RESERVED(x)                (((x) & 0xFF) << 8)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_RESERVEDO(x)               (((x) & 0xFF))

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_TEST */

#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TESTDIN(x)                 (((x) & 0xFF) << 11)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TESTDOUT(x)                (((x) & 0xFF) << 3)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TESTEN                     BIT(2)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TESTCLK                    BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TESTCLR                    BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_DATALANE_CTRL */

#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TURNREQUEST_0              BIT(22)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_DIRECTION_0                BIT(21)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TURNDISABLE_0              BIT(20)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_FORCERXMODE_0              BIT(19)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_FORCETXSTOPMODE_0          BIT(18)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_STOPSTATEDATA_0            BIT(17)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TURNREQUEST_1              BIT(16)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TURNDISABLE_1              BIT(15)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_FORCERXMODE_1              BIT(14)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_FORCETXSTOPMODE_1          BIT(13)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_STOPSTATEDATA_1            BIT(12)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TURNREQUEST_2              BIT(11)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_DIRECTION_2                BIT(10)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TURNDISABLE_2              BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_FORCERXMODE_2              BIT(8)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_FORCETXSTOPMODE_2          BIT(7)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_STOPSTATEDATA_2            BIT(6)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TURNREQUEST_3              BIT(5)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_DIRECTION_3                BIT(4)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_TURNDISABLE_3              BIT(3)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_FORCERXMODE_3              BIT(2)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_FORCETXSTOPMODE_3          BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_STOPSTATEDATA_3            BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_DUMY_CTRL */

#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_ANALOG_DSI_DUMY_IN(x)          (((x) & 0xFFFF) << 16)
#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_ANALOG_DSI_DUMY_OUT(x)         (((x) & 0xFFFF))

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTHSCLK     BIT(31)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSCLK          BIT(30)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXITCLK      BIT(29)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_0  BIT(28)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_0     BIT(27)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXLPDTESC_0        BIT(26)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_0        BIT(25)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_0       BIT(24)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXTRIGGERESC_0     BIT(23)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXVALIDESC_0       BIT(22)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_1  BIT(21)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_1     BIT(20)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXLPDTESC_1        BIT(19)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_1        BIT(18)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_1       BIT(17)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXTRIGGERESC_1     BIT(16)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXVALIDESC_1       BIT(15)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_2  BIT(14)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_2     BIT(13)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXLPDTESC_2        BIT(12)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_2        BIT(11)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_2       BIT(10)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXTRIGGERESC_2     BIT(9)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXVALIDESC_2       BIT(8)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_3  BIT(7)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_3     BIT(6)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXLPDTESC_3        BIT(5)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_3        BIT(4)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_3       BIT(3)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXTRIGGERESC_3     BIT(2)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXVALIDESC_3       BIT(1)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXDATAESC_0        BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_REG_SEL_CFG_1 */

#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_ISO_SW_EN          BIT(19)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXDATAESC_1        BIT(18)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXDATAESC_2        BIT(17)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXDATAESC_3        BIT(16)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_PS_PD_S            BIT(15)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_PS_PD_L            BIT(14)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_SHUTDOWNZ          BIT(13)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_RSTZ               BIT(12)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_0           BIT(11)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_1           BIT(10)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_2           BIT(9)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_3           BIT(8)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_ENABLECLK          BIT(7)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_FORCEPLL           BIT(6)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_BISTON             BIT(5)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TESTDIN            BIT(4)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TESTEN             BIT(3)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TESTCLK            BIT(2)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TESTCLR            BIT(1)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TURNREQUEST_0      BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_USB20_USB20_TEST_PIN */

#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TESTCLK                           BIT(24)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TESTDATAIN(x)                     (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TESTADDR(x)                       (((x) & 0xF) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TESTDATAOUTSEL                    BIT(11)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TESTDATAOUT(x)                    (((x) & 0xF) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_BIST_MODE(x)                      (((x) & 0x1F) << 2)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_T2RCOMP                           BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_LPBK_END                          BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_USB20_USB20_UTMI_CTL1 */

#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_DATABUS16_8                       BIT(28)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_SUSPENDM                          BIT(27)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_PORN                              BIT(26)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_RESET                             BIT(25)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_RXERROR                           BIT(24)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_BYPASS_DRV_DP                     BIT(23)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_BYPASS_DRV_DM                     BIT(22)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_BYPASS_FS                         BIT(21)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_BYPASS_IN_DP                      BIT(20)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_BYPASS_IN_DM                      BIT(19)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_BYPASS_OUT_DP                     BIT(18)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_BYPASS_OUT_DM                     BIT(17)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_VBUSVLDEXT                        BIT(16)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_RESERVED(x)                       (((x) & 0xFFFF))

/* REG_ANLG_PHY_G4_ANALOG_USB20_USB20_BATTER_PLL */

#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_PS_PD_S                           BIT(5)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_PS_PD_L                           BIT(4)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_REXTENABLE                        BIT(3)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_DMPULLUP                          BIT(2)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_HSIC_PLLON                              BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_SAMPLER_SEL                       BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_USB20_USB20_UTMI_CTL2 */

#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_DPPULLDOWN                        BIT(3)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_DMPULLDOWN                        BIT(2)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TXBITSTUFFENABLE                  BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TXBITSTUFFENABLEH                 BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_USB20_USB20_TRIMMING */

#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TUNEHSAMP(x)                      (((x) & 0x3) << 27)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TFREGRES(x)                       (((x) & 0x3F) << 21)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TFHSRES(x)                        (((x) & 0x1F) << 16)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TUNERISE(x)                       (((x) & 0x3) << 14)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TUNEOTG(x)                        (((x) & 0x7) << 11)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TUNEDSC(x)                        (((x) & 0x3) << 9)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TUNESQ(x)                         (((x) & 0xF) << 5)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TUNEEQ(x)                         (((x) & 0x7) << 2)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_TUNEPLLS(x)                       (((x) & 0x3))

/* REG_ANLG_PHY_G4_ANALOG_USB20_USB20_PHY_BIST_TEST */

#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_BISTRAM_EN                        BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_USB20_USB20_BIST_MODE_EN                      BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_USB20_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_USB20_USB20_SUSPENDM                  BIT(9)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_USB20_USB20_PORN                      BIT(8)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_USB20_USB20_RESET                     BIT(7)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_USB20_USB20_BYPASS_FS                 BIT(6)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_USB20_USB20_BYPASS_IN_DM              BIT(5)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_USB20_USB20_PS_PD_S                   BIT(4)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_USB20_USB20_PS_PD_L                   BIT(3)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_USB20_USB20_DMPULLUP                  BIT(2)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_USB20_USB20_DPPULLDOWN                BIT(1)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_USB20_USB20_DMPULLDOWN                BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_RCO100M_RTC100M_CTRL */

#define BIT_ANLG_PHY_G4_ANALOG_RCO100M_RTC100M_RESERVED(x)                   (((x) & 0xFF) << 15)
#define BIT_ANLG_PHY_G4_ANALOG_RCO100M_RTC100M_LDO_EN                        BIT(14)
#define BIT_ANLG_PHY_G4_ANALOG_RCO100M_RTC100M_LDO_BYPASS                    BIT(13)
#define BIT_ANLG_PHY_G4_ANALOG_RCO100M_RTC100M_LDO_VOLTAGE_SEL(x)            (((x) & 0x3) << 11)
#define BIT_ANLG_PHY_G4_ANALOG_RCO100M_RTC100M_LDO_BIAS_SEL(x)               (((x) & 0x3) << 9)
#define BIT_ANLG_PHY_G4_ANALOG_RCO100M_RTC100M_RC_C(x)                       (((x) & 0x7F) << 2)
#define BIT_ANLG_PHY_G4_ANALOG_RCO100M_RTC100M_EN                            BIT(1)
#define BIT_ANLG_PHY_G4_ANALOG_RCO100M_RTC100M_RSTB                          BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_RCO100M_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_RCO100M_RTC100M_RC_C                  BIT(2)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_RCO100M_RTC100M_EN                    BIT(1)
#define BIT_ANLG_PHY_G4_DBG_SEL_ANALOG_RCO100M_RTC100M_RSTB                  BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_USB20_IDDG */

#define BIT_ANLG_PHY_G4_ANALOG_USB20_UTMIOTG_IDDG                            BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_4L_ISO_SW_EN */

#define BIT_ANLG_PHY_G4_ANALOG_MIPI_DSI_4LANE_DSI_ISO_SW_EN                  BIT(0)

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_0 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_RESERVED_DVFS_0(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_IBIAS_DVFS_0(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV_DVFS_0             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_KINT_DVFS_0(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_NINT_DVFS_0(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_1 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_RESERVED_DVFS_1(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_IBIAS_DVFS_1(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV_DVFS_1             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_KINT_DVFS_1(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_NINT_DVFS_1(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_2 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_RESERVED_DVFS_2(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_IBIAS_DVFS_2(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV_DVFS_2             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_KINT_DVFS_2(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_NINT_DVFS_2(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_3 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_RESERVED_DVFS_3(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_IBIAS_DVFS_3(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV_DVFS_3             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_KINT_DVFS_3(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_NINT_DVFS_3(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_4 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_RESERVED_DVFS_4(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_IBIAS_DVFS_4(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV_DVFS_4             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_KINT_DVFS_4(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_NINT_DVFS_4(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_5 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_RESERVED_DVFS_5(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_IBIAS_DVFS_5(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV_DVFS_5             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_KINT_DVFS_5(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL0_NINT_DVFS_5(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_0 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_RESERVED_DVFS_0(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_IBIAS_DVFS_0(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV_DVFS_0             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_KINT_DVFS_0(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_NINT_DVFS_0(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_1 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_RESERVED_DVFS_1(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_IBIAS_DVFS_1(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV_DVFS_1             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_KINT_DVFS_1(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_NINT_DVFS_1(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_2 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_RESERVED_DVFS_2(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_IBIAS_DVFS_2(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV_DVFS_2             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_KINT_DVFS_2(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_NINT_DVFS_2(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_3 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_RESERVED_DVFS_3(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_IBIAS_DVFS_3(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV_DVFS_3             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_KINT_DVFS_3(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_NINT_DVFS_3(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_4 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_RESERVED_DVFS_4(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_IBIAS_DVFS_4(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV_DVFS_4             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_KINT_DVFS_4(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_NINT_DVFS_4(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_5 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_RESERVED_DVFS_5(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_IBIAS_DVFS_5(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV_DVFS_5             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_KINT_DVFS_5(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL1_NINT_DVFS_5(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_DVFS_0 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_RESERVED_DVFS_0(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_IBIAS_DVFS_0(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_POSTDIV_DVFS_0             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_KINT_DVFS_0(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_NINT_DVFS_0(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_DVFS_1 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_RESERVED_DVFS_1(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_IBIAS_DVFS_1(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_POSTDIV_DVFS_1             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_KINT_DVFS_1(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_NINT_DVFS_1(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_DVFS_2 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_RESERVED_DVFS_2(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_IBIAS_DVFS_2(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_POSTDIV_DVFS_2             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_KINT_DVFS_2(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_NINT_DVFS_2(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_DVFS_3 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_RESERVED_DVFS_3(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_IBIAS_DVFS_3(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_POSTDIV_DVFS_3             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_KINT_DVFS_3(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_NINT_DVFS_3(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_DVFS_4 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_RESERVED_DVFS_4(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_IBIAS_DVFS_4(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_POSTDIV_DVFS_4             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_KINT_DVFS_4(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_NINT_DVFS_4(x)             (((x) & 0x7F))

/* REG_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_DVFS_5 */

#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_RESERVED_DVFS_5(x)         (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_IBIAS_DVFS_5(x)            (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_POSTDIV_DVFS_5             BIT(9)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_KINT_DVFS_5(x)             (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G4_ANALOG_MPLL_THM_TOP_MPLL2_NINT_DVFS_5(x)             (((x) & 0x7F))


#endif /* ANLG_PHY_G4_H */

